1. Field of the Invention
This invention generally relates to a semiconductor device and in particular to a programmable logic array (hereinafter also referred to as "PLA"). More specifically, the present invention relates to an erasable field programmable logic array (erasable FPLA) including an array of memory cells which may be selectively programmed to store or unprogrammed to erase a combinational logic whether it is sequential or not.
2. Description of the Prior Art
The programmable logic array (PLA) is well known in the art, and it is a structure that has all the generality of a memory for implementing combinational logic functions. A PLA is becoming more popular because it can be far more compact than a ROM implementation for the same logic function if the PLA layout is appropriately determined.
A programmable logic array or field programmable logic array is a logic array including an array of logic gates whose internal connections may be programmed by the end user. That is, a typical PLA or FPLA includes a matrix of conducting paths and alterable memory elements, such as fusible links, diodes and bipolar transistors, each disposed at the intersections of the conducting paths. Thus, these memory elements may be selectively programmed to possess either one of the binary data thereby forming a desired logic circuit using appropriate gates such as AND, OR, NAND, NOR, etc. However, prior art PLAs or FPLAs are limited in that once the memory elements have been programmed, they can not be altered because programming is carried out by altering the state of the selected memory elements permanently.